About the Opportunity 

We are looking for a master's student to write their thesis on AI-assisted test generation for SoC IP verification. Working with our verification team, you will explore how AI can automate hardware test development and improve verification efficiency. 

Below are some examples of parts that could be included in the thesis work:

• Literature study of different generative AI Models in hardware verification (mandatory)
• Building AI-assisted test generation using large language models (mandatory)
• Comparing AI-generated vs manual tests for coverage and bug detection (mandatory)
• Implementation and testing in higher-level subsytems including top (optional) This is an opportunity to work at the intersection of AI and semiconductor verification while gaining hands-on experience with industrial verification flows.

About the Thesis Work 

Manual verification test development is time-intensive and requires deep expertise. This thesis evaluates AI's potential to generate effective verification tests for SoC IP blocks. You’ll be involved in creation of reusable AI-assisted verification methodology to be reused 

Key Qualifications

• You are ready to start writing your master's thesis in electrical engineering, computer engineering or similar in January 2026 or earlier Dec'25
• Programming experience (C/SystemVerilog/Python preferred)
• An interest in digital design and verification methodologies (UVM)
• Familiarity with AI/ML concepts is beneficial 
• Self motivated and eager to learn with minimal guidance Practical Details • Duration: January - Sep 2026 (can be extened upto 9 months)

If you are interested in working with us, send us a motivational letter where you share your motivation and interest in AI-assisted verification. Please remember to attach your latest grades.

Practical details

• Location: Tampere, FInland (on-site)
  

Please note that this position might be subject to a background check.